Difference between revisions of "Reverse engineering ZIOVA CS615"

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(Added dumps)
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= Inside =
 
= Inside =
[[File:ZIOVA_CS615_outside.jpg|200px]]<br>
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[[File:ZIOVA_CS615_outside.jpg|200px]]
[[File:ZIOVA_CS615_inside.jpg|200px]]<br>
+
[[File:ZIOVA_CS615_inside.jpg|200px]]
[[File:ZIOVA_CS615_pins.jpg|200px]]<br>
+
[[File:ZIOVA_CS615_pins.jpg|200px]]
  
 
== Pinout UART ==
 
== Pinout UART ==
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 +
  
 
= Hardware =
 
= Hardware =

Revision as of 21:53, 8 May 2012

Inside

ZIOVA CS615 outside.jpg ZIOVA CS615 inside.jpg ZIOVA CS615 pins.jpg

Pinout UART

Hardware

CS615[bin]$ cat /proc/cpuinfo system type : Sigma Designs TangoX processor : 0 cpu model : MIPS 4KEc V6.9 Initial BogoMIPS : 291.84 wait instruction : yes microsecond timers : yes tlb_entries : 32 extra interrupt vector : yes hardware watchpoint : yes ASEs implemented : mips16 VCED exceptions : not available VCEI exceptions : not available System bus frequency : 198000000 Hz CPU frequency : 297000000 Hz DSP frequency : 297000000 Hz

Dumps

ZIOVA CS615 boot