Difference between revisions of "Reverse engineering ZIOVA CS615"

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(Pinout UART)
(proper dumps)
Line 17: Line 17:
  
 
= Hardware =
 
= Hardware =
 +
<pre>
 
CS615[bin]$ cat /proc/cpuinfo
 
CS615[bin]$ cat /proc/cpuinfo
 
system type : Sigma Designs TangoX
 
system type : Sigma Designs TangoX
Line 33: Line 34:
 
CPU frequency : 297000000 Hz
 
CPU frequency : 297000000 Hz
 
DSP frequency : 297000000 Hz
 
DSP frequency : 297000000 Hz
 
+
</pre>
 
=Dumps=
 
=Dumps=
 
[[ZIOVA CS615 boot]]
 
[[ZIOVA CS615 boot]]

Revision as of 23:52, 8 May 2012

Inside

ZIOVA CS615 outside.jpg ZIOVA CS615 inside.jpg ZIOVA CS615 pins.jpg

Pinout UART

X  X  TX  X  GND
.  X  RX  X   X

X:pin
.:nopin
TX: Transmit (box)
RX: Read (box)
GND: Ground

Hardware

CS615[bin]$ cat /proc/cpuinfo
system type		: Sigma Designs TangoX
processor		: 0
cpu model		: MIPS 4KEc V6.9
Initial BogoMIPS	: 291.84
wait instruction	: yes
microsecond timers	: yes
tlb_entries		: 32
extra interrupt vector	: yes
hardware watchpoint	: yes
ASEs implemented	: mips16
VCED exceptions		: not available
VCEI exceptions		: not available
System bus frequency	: 198000000 Hz
CPU frequency		: 297000000 Hz
DSP frequency		: 297000000 Hz

Dumps

ZIOVA CS615 boot